The present disclosure relates to a semiconductor device having a metal gate electrode and a method for fabricating the same.
Referring to FIGS. 19A-19F, a description will be given to a method for forming a metal-inserted polysilicon stack (so-called MIPS) structure in which a metal material and polysilicon are laminated and which is among metal gate structures in conventional metal insulator semiconductor (MIS) transistors (see, e.g., Patent Document 1).
First, as shown in FIG. 19A, an isolation film 102 formed of shallow trench isolation (STI) or the like is selectively formed in an upper portion of a semiconductor substrate 101 made of silicon to partition the semiconductor substrate 101 into an N-type field effect transistor (NFET) formation region 50N and a P-type field effect transistor (PFET) formation region 50P. Then, impurity implantation for threshold (Vt) control and a heat treatment for activating implanted impurities are performed. Subsequently, a gate insulating film 103 is formed over the entire surface of the semiconductor substrate 101. Subsequently, over the entire surface of the formed gate insulating film 103, a titanium nitride (TiN) film 104 is deposited which has a high work function, and is effective for the operation characteristics of the PFET. Thereafter, the portion of the deposited TiN film 104 included in the NFET formation region 50N is removed.
Next, as shown in FIG. 19B, a polysilicon film 105 is deposited over the entire surfaces of the NFET formation region 50N and the PFET formation region 50P.
Next, as shown in FIG. 19C, a tungsten (W) film 106, which is a refractory metal, and a silicon nitride (SiN) film 107 are successively deposited over the polysilicon film 105.
Next, as shown in FIG. 19D, the plurality of deposited films are patterned to form a gate electrode 120. Specifically, in the NFET formation region 50N, a first gate electrode portion 120a including the W film 106 and the polysilicon film 105 is formed as the gate electrode 120. In the PFET formation region 50P, a second gate electrode portion 120b including the W film 106, the polysilicon film 105, and the TiN film 104 is formed as the gate electrode 120. Here, there is shown a cross section of the gate electrode 120 along the gate width direction thereof.
Next, as shown in FIG. 19E, a lightly doped drain (LDD) layer is formed by performing extension implantation on the semiconductor substrate 101 using the gate electrode 120 as a mask, and sidewalls 108 are formed on the side surfaces of the gate electrode 120. Then, using the gate electrode 120 and the sidewalls 108 as a mask, source/drain implantation is performed on the semiconductor substrate 101, and a heat treatment for activating the implanted impurity is performed. Thereafter, a nickel (Ni) film is deposited over the entire surface of the semiconductor substrate 101 and predetermined some heat treatment is performed to form a nickel silicide layer 109 on each of source/drain regions.
Next, as shown in FIG. 19F, an interlayer insulating film 110 is deposited over the semiconductor substrate 101, and the upper surface of the deposited interlayer insulating film 110 is planarized. Subsequently, a contact hole is formed in the planarized interlayer insulating film 110 and in the SiN film 107 located on the gate electrode 120 to expose the underlying W film 106. By filling the contact hole with tungsten (W), a contact 111 is formed.
In this manner, a metal gate having the MIPS structure is formed in the PFET formation region 50P, while a polysilicon gate is formed in the NFET formation region 50N.    Patent Document 1: Japanese Laid-Open Patent Publication No. 2007-088122    Patent Document 2: Japanese Laid-Open Patent Publication No. 2001-274391